1. Lovely Professional University
  2. Ph.D Thesis
  3. Ph.D Thesis
Please use this identifier to cite or link to this item: http://localhost:8080/xmlui/handle/123456789/4642
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dc.contributor.authorSharma, Rajkumar-
dc.contributor.authorBhargava, Cherry-
dc.contributor.authorJain, Shruti-
dc.date.accessioned2024-02-23T05:41:51Z-
dc.date.available2024-02-23T05:41:51Z-
dc.date.issued2020-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/4642-
dc.language.isoen_USen_US
dc.publisherLovely Professional University, Phagwaraen_US
dc.subjectElectronics and Electrical Engineeringen_US
dc.titleDesign and anaysis of a novel hybrid 8 x 8 BIT multiply and accumulate (MAC) architecture using clock gating scheme for pipelined processingen_US
dc.typeThesisen_US
Appears in Collections:Ph.D Thesis

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