1. Lovely Professional University
  2. Ph.D Thesis
  3. Ph.D Thesis
Please use this identifier to cite or link to this item: http://localhost:8080/xmlui/handle/123456789/8092
Title: Development of arithmetic algorithm and design of architecture level multiplier for fast and efficient computations on fpga
Authors: Bhandari, Jugal Kishore
Verma, Yogesh Kumar
Keywords: Electronics and Communication Engineering
Issue Date: 2024
Publisher: Lovely Professional University,Phagwara
URI: http://localhost:8080/xmlui/handle/123456789/8092
Appears in Collections:Ph.D Thesis

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