1. Lovely Professional University
  2. Ph.D Thesis
  3. Ph.D Thesis
Please use this identifier to cite or link to this item: http://localhost:8080/xmlui/handle/123456789/8092
Full metadata record
DC FieldValueLanguage
dc.contributor.authorBhandari, Jugal Kishore-
dc.contributor.authorVerma, Yogesh Kumar-
dc.date.accessioned2026-04-01T10:36:25Z-
dc.date.available2026-04-01T10:36:25Z-
dc.date.issued2024-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/8092-
dc.language.isoen_USen_US
dc.publisherLovely Professional University,Phagwaraen_US
dc.subjectElectronics and Communication Engineeringen_US
dc.titleDevelopment of arithmetic algorithm and design of architecture level multiplier for fast and efficient computations on fpgaen_US
dc.typeThesisen_US
Appears in Collections:Ph.D Thesis

Files in This Item:
File Description SizeFormat 
Full Thesis_42000123_V2.pdf2.51 MBAdobe PDFView/Open
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.